Single step appears to work.

[riscv-isa-sim.git] / riscv / insns / dret.h

diff --git a/riscv/insns/dret.h b/riscv/insns/dret.h
index 6cfd1e2660496c2bf137bb64188ad78b7b84a346..35c19cb8a29090b774ff8c7a1fa091aa36428e21 100644 (file)
--- a/riscv/insns/dret.h
+++ b/riscv/insns/dret.h
@@ -4,3 +4,6 @@ p->set_privilege(STATE.dcsr.prv);
 
 /* We're not in Debug Mode anymore. */
 STATE.dcsr.cause = 0;
+
+if (STATE.dcsr.step)
+  STATE.single_step = STATE.STEP_STEPPING;