Implement Q extension

[riscv-isa-sim.git] / riscv / insns / fmv_x_w.h

diff --git a/riscv/insns/fmv_x_w.h b/riscv/insns/fmv_x_w.h
index b72247958c762237a2316ab7ed7f4a9d29eaf1fd..6754f8693f329bc16faed03f54c4481dbb305a56 100644 (file)
--- a/riscv/insns/fmv_x_w.h
+++ b/riscv/insns/fmv_x_w.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_RD(sext32(FRS1.v));
+WRITE_RD(sext32(FRS1.v[0]));