Upgrade to latest SoftFloat
[riscv-isa-sim.git] / riscv / insns / fnmsub_s.h
index 3be27d09b5f01d952855d024a9cf1ca4ae4e06d6..3e0b8ea7ce37c85e1c6220fdefcc717e0a9cd9ba 100644 (file)
@@ -1,5 +1,5 @@
 require_extension('F');
 require_fp;
 softfloat_roundingMode = RM;
-WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
+WRITE_FRD(f32_mulAdd(f32(FRS1 ^ (uint32_t)INT32_MIN), f32(FRS2), f32(FRS3)).v);
 set_fp_exceptions;