[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / jalr_c.h

diff --git a/riscv/insns/jalr_c.h b/riscv/insns/jalr_c.h
index 18b2508ec898357e17538366c4bd7baced9fc6d0..dade874cb807d6de6d11c4158d8de1d12d1da4af 100644 (file)
--- a/riscv/insns/jalr_c.h
+++ b/riscv/insns/jalr_c.h
@@ -1,3 +1,3 @@
 uint32_t temp = npc;
-npc = RA;
-RC = temp;
+npc = RS1;
+RDR = temp;