[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / lw.h

diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index e1f56fefa00308e3b479b883e80fa447f022f55f..6bd26463adba7445d6b2cc1569bbc4b9f4520edd 100644 (file)
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-RA = mmu.load_int32(RB+SIMM);
+RDI = mmu.load_int32(RS1+SIMM);