[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mffh_d.h

diff --git a/riscv/insns/mffh_d.h b/riscv/insns/mffh_d.h
index b466f60c86a8f9a886ab11a58aad8ab65bcd8081..45dd36ac1ca75b212b252c401164484f01a5c949 100644 (file)
--- a/riscv/insns/mffh_d.h
+++ b/riscv/insns/mffh_d.h
@@ -1,2 +1,2 @@
 require_fp;
-RC = sext32(FRA >> 32);
+RDR = sext32(FRS1 >> 32);