[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / mul.h

diff --git a/riscv/insns/mul.h b/riscv/insns/mul.h
index 9c81285022b4746fcf57329f5a1b82260f7b25e0..226873f9c883917f468b4b44e056b56d39ba7fc4 100644 (file)
--- a/riscv/insns/mul.h
+++ b/riscv/insns/mul.h
@@ -1,2 +1,2 @@
 require64;
-RC = RA * RB;
+RDR = RS1 * RS2;