[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / or.h

diff --git a/riscv/insns/or.h b/riscv/insns/or.h
index d88c9f84e7c2c97856ec83b4f436af12c7d85920..ef27ba6f25a0c27606ac9fa120200db9d021bc56 100644 (file)
--- a/riscv/insns/or.h
+++ b/riscv/insns/or.h
@@ -1 +1 @@
-RC = RA | RB;
+RDR = RS1 | RS2;