[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / remw.h

diff --git a/riscv/insns/remw.h b/riscv/insns/remw.h
index 1bb3051d9692d4d3d7d70fd4bf508cd06225ab0c..83bf1470265104267fb33ddc57b0aeea39855c81 100644 (file)
--- a/riscv/insns/remw.h
+++ b/riscv/insns/remw.h
@@ -1,2 +1,2 @@
-RC = sext32(int32_t(RA) % int32_t(RB));
+RDR = sext32(int32_t(RS1) % int32_t(RS2));