Instructions are no longer member functions

[riscv-isa-sim.git] / riscv / insns / sc_d.h

diff --git a/riscv/insns/sc_d.h b/riscv/insns/sc_d.h
index a29b9f74f4bc971a08c068638ce0db82d0751067..9ad962c6bd810736e1baf2885eba19da89a3d18d 100644 (file)
--- a/riscv/insns/sc_d.h
+++ b/riscv/insns/sc_d.h
@@ -1,2 +1,8 @@
 require_xpr64;
-RD = mmu.store_conditional_uint64(RS1, RS2);
+if (RS1 == p->get_state()->load_reservation)
+{
+  MMU.store_uint64(RS1, RS2);
+  RD = 0;
+}
+else
+  RD = 1;