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Instructions are no longer member functions
[riscv-isa-sim.git]
/
riscv
/
insns
/
sc_w.h
diff --git
a/riscv/insns/sc_w.h
b/riscv/insns/sc_w.h
index caf768340215dfe9744bdebc64c7459705201d44..3ad79ac24f72241877530ddb8ed9e9bb2d98774c 100644
(file)
--- a/
riscv/insns/sc_w.h
+++ b/
riscv/insns/sc_w.h
@@
-1
+1,7
@@
-RD = mmu.store_conditional_uint32(RS1, RS2);
+if (RS1 == p->get_state()->load_reservation)
+{
+ MMU.store_uint32(RS1, RS2);
+ RD = 0;
+}
+else
+ RD = 1;