[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sd.h

diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
index 6a698ee8f7e34942c9685cc8f066ea47c95ba819..587df8df47ce21f621d1bb2203e85fb67e58550d 100644 (file)
--- a/riscv/insns/sd.h
+++ b/riscv/insns/sd.h
@@ -1,2 +1,2 @@
 require64;
-mmu.store_uint64(RB+SIMM, RA);
+mmu.store_uint64(RS1+SIMM, RS2);