[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / sgninj_s.h

diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h
index b68817711c0ed9cf60270b5d7d8c6d7e293b4d88..2df0b94a0e654535b2815f5c5e221cdb4606746f 100644 (file)
--- a/riscv/insns/sgninj_s.h
+++ b/riscv/insns/sgninj_s.h
@@ -1,2 +1,2 @@
 require_fp;
-FRC = (FRA &~ (uint32_t)INT32_MIN) | (FRB & (uint32_t)INT32_MIN);
+FRDR = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);