[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / slt.h

diff --git a/riscv/insns/slt.h b/riscv/insns/slt.h
index ccc1d447ea6deac67f9aedf67af49d2b02918153..6511f42c838485013e8034f473fd034cc5d98597 100644 (file)
--- a/riscv/insns/slt.h
+++ b/riscv/insns/slt.h
@@ -1 +1 @@
-RC = sreg_t(cmp_trunc(RA)) < sreg_t(cmp_trunc(RB));
+RDR = sreg_t(cmp_trunc(RS1)) < sreg_t(cmp_trunc(RS2));