[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / truncu_l_s.h

diff --git a/riscv/insns/truncu_l_s.h b/riscv/insns/truncu_l_s.h
index 5d5a9408e31b70d89c7f613ca63cda865572011d..1d48192162e191541c673f91ebe0c41e4eeb2dad 100644 (file)
--- a/riscv/insns/truncu_l_s.h
+++ b/riscv/insns/truncu_l_s.h
@@ -1,3 +1,3 @@
 require_fp;
-FRC = f32_to_i64_r_minMag(FRA,true);
+FRDR = f32_to_i64_r_minMag(FRS1,true);
 set_fp_exceptions;