[sim,opcodes] improved sim build and run performance

[riscv-isa-sim.git] / riscv / insns / vf.h

diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
index c3a43cf4b627510267e9303fbef1c46821b3180b..777964544e3c1cd9f978ae8a3be38ec50d21de53 100644 (file)
--- a/riscv/insns/vf.h
+++ b/riscv/insns/vf.h
@@ -4,5 +4,5 @@ for (int i=0; i<VL; i++)
   uts[i]->pc = RS1+SIMM;
   uts[i]->utmode = true;
   while (uts[i]->utmode)
-    uts[i]->step(n, noisy);
+    uts[i]->step(1, false); // XXX
 }