[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / xor.h

diff --git a/riscv/insns/xor.h b/riscv/insns/xor.h
index 9d024472359e340b3f5083aa366263d3a71bb7e6..f11738a05b1e144c913a06a64994a5fc0f9fe881 100644 (file)
--- a/riscv/insns/xor.h
+++ b/riscv/insns/xor.h
@@ -1 +1 @@
-RC = RA ^ RB;
+RDR = RS1 ^ RS2;