[xcc, sim] changed instruction format so imm12 subs for rs2

[riscv-isa-sim.git] / riscv / insns / xori.h

diff --git a/riscv/insns/xori.h b/riscv/insns/xori.h
index 5ca46377d7386f9ba59e10d6660906c38928c0a2..fcf90429a264b3dce641961cab225aad2d96e9ad 100644 (file)
--- a/riscv/insns/xori.h
+++ b/riscv/insns/xori.h
@@ -1 +1 @@
-RA = IMM ^ RB;
+RDI = IMM ^ RS1;