Exceptions in Debug Mode, stay in Debug Mode.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index d937f2e481293cb7cceafdcffbaafb885e93e271..7f3ba421caab0cc87472780eb9d8cbf6d1be235d 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -236,7 +236,11 @@ void processor_t::take_trap(trap_t& t, reg_t epc)
     set_csr(CSR_MSTATUS, s);
     set_privilege(PRV_S);
   } else {
-    state.pc = state.mtvec;
+    if (state.dcsr.cause) {
+      state.pc = DEBUG_ROM_EXCEPTION;
+    } else {
+      state.pc = state.mtvec;
+    }
     state.mcause = t.cause();
     state.mepc = epc;
     if (t.has_badaddr())