Add dret.

[riscv-isa-sim.git] / riscv / processor.cc

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f09eea8f6c64e9289c52483f5595b008d261bc0d..f98d0a090e139deab65d1a61f7ca7009864d0cce 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -198,7 +198,7 @@ void processor_t::enter_debug_mode(uint8_t cause)
   fprintf(stderr, "enter_debug_mode(%d)\n", cause);
   state.dcsr.cause = cause;
   state.dcsr.prv = state.prv;
-  state.prv = PRV_M;
+  set_privilege(PRV_M);
   state.dpc = state.pc;
   state.pc = DEBUG_ROM_START;
   debug = true; // TODO