Single step appears to work.

[riscv-isa-sim.git] / riscv / processor.h

diff --git a/riscv/processor.h b/riscv/processor.h
index 9c2f7a66aa1da730fc72bcabeb54c983bbc1c831..721da2cb54fdb53f0611e6e6b97097bbefdb38f4 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -81,6 +81,14 @@ struct state_t
   uint32_t frm;
   bool serialized; // whether timer CSRs are in a well-defined state
 
+  // When true, execute a single instruction and then enter debug mode.  This
+  // can only be set by executing dret.
+  enum {
+      STEP_NONE,
+      STEP_STEPPING,
+      STEP_STEPPED
+  } single_step;
+
   reg_t load_reservation;
 
 #ifdef RISCV_ENABLE_COMMITLOG