Remove more vector stuff

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 687d5bca6aaf2a47a6105d0d8a1e59e89ec2963e..335a0bfb2ba69ae97b4dbc92ff97f1e1645758f4 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -20,13 +20,3 @@ AC_ARG_ENABLE([64bit], AS_HELP_STRING([--disable-64bit], [Disable 64-bit mode]))
 AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
 ])
-
-AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression]))
-AS_IF([test "x$enable_rvc" = "xyes"], [
-  AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
-])
-
-AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor]))
-AS_IF([test "x$enable_vec" != "xno"], [
-  AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
-])