[sim] add disable option for vector

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 9bb4f2faacdce74b83b058fb6da06367299c0b18..36c701a484851cedc8f5b1032b2814944bca0151 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -13,6 +13,11 @@ AS_IF([test "x$enable_rvc" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
 ])
 
+AC_ARG_ENABLE([vec], AS_HELP_STRING([--disable-vec], [Disable vector processor]))
+AS_IF([test "x$enable_vec" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])