[sim,pk] reorganized status register

[riscv-isa-sim.git] / riscv / riscv.ac

diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 7898145098c70b75f829bf5b114a500051576ccf..9bb4f2faacdce74b83b058fb6da06367299c0b18 100644 (file)
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -8,6 +8,11 @@ AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
 ])
 
+AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable instruction compression]))
+AS_IF([test "x$enable_rvc" != "xno"], [
+  AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
+])
+
 libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
 AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])