[sim] added icache simulator (disabled by default)

[riscv-isa-sim.git] / riscv / riscv.mk.in

diff --git a/riscv/riscv.mk.in b/riscv/riscv.mk.in
index 6d55c8033876d848c66c85cfd0db6f511d10caa3..f53bc13335d79817f07b2f72b07aa3ecde1ce63b 100644 (file)
--- a/riscv/riscv.mk.in
+++ b/riscv/riscv.mk.in
@@ -18,6 +18,7 @@ riscv_srcs = \
        processor.cc \
        sim.cc \
        trap.cc \
+       icsim.cc \
 
 riscv_test_srcs =