#include "sim.h"
#include "mmu.h"
+#include "dts.h"
#include "remote_bitbang.h"
#include <map>
#include <iostream>
std::vector<std::pair<reg_t, mem_t*>> mems,
const std::vector<std::string>& args,
std::vector<int> const hartids, unsigned progsize,
- unsigned max_bus_master_bits)
+ unsigned max_bus_master_bits, bool require_authentication)
: htif_t(args), mems(mems), procs(std::max(nprocs, size_t(1))),
start_pc(start_pc), current_step(0), current_proc(0), debug(false),
- remote_bitbang(NULL), debug_module(this, progsize, max_bus_master_bits)
+ histogram_enabled(false), dtb_enabled(true), remote_bitbang(NULL),
+ debug_module(this, progsize, max_bus_master_bits, require_authentication)
{
signal(SIGINT, &handle_signal);
if (current_step == INTERLEAVE)
{
current_step = 0;
- procs[current_proc]->yield_load_reservation();
+ procs[current_proc]->get_mmu()->yield_load_reservation();
if (++current_proc == procs.size()) {
current_proc = 0;
clint->increment(INTERLEAVE / INSNS_PER_RTC_TICK);
return bus.store(addr, len, bytes);
}
-static std::string dts_compile(const std::string& dts)
-{
- // Convert the DTS to DTB
- int dts_pipe[2];
- pid_t dts_pid;
-
- if (pipe(dts_pipe) != 0 || (dts_pid = fork()) < 0) {
- std::cerr << "Failed to fork dts child: " << strerror(errno) << std::endl;
- exit(1);
- }
-
- // Child process to output dts
- if (dts_pid == 0) {
- close(dts_pipe[0]);
- int step, len = dts.length();
- const char *buf = dts.c_str();
- for (int done = 0; done < len; done += step) {
- step = write(dts_pipe[1], buf+done, len-done);
- if (step == -1) {
- std::cerr << "Failed to write dts: " << strerror(errno) << std::endl;
- exit(1);
- }
- }
- close(dts_pipe[1]);
- exit(0);
- }
-
- pid_t dtb_pid;
- int dtb_pipe[2];
- if (pipe(dtb_pipe) != 0 || (dtb_pid = fork()) < 0) {
- std::cerr << "Failed to fork dtb child: " << strerror(errno) << std::endl;
- exit(1);
- }
-
- // Child process to output dtb
- if (dtb_pid == 0) {
- dup2(dts_pipe[0], 0);
- dup2(dtb_pipe[1], 1);
- close(dts_pipe[0]);
- close(dts_pipe[1]);
- close(dtb_pipe[0]);
- close(dtb_pipe[1]);
- execl(DTC, DTC, "-O", "dtb", 0);
- std::cerr << "Failed to run " DTC ": " << strerror(errno) << std::endl;
- exit(1);
- }
-
- close(dts_pipe[1]);
- close(dts_pipe[0]);
- close(dtb_pipe[1]);
-
- // Read-out dtb
- std::stringstream dtb;
-
- int got;
- char buf[4096];
- while ((got = read(dtb_pipe[0], buf, sizeof(buf))) > 0) {
- dtb.write(buf, got);
- }
- if (got == -1) {
- std::cerr << "Failed to read dtb: " << strerror(errno) << std::endl;
- exit(1);
- }
- close(dtb_pipe[0]);
-
- // Reap children
- int status;
- waitpid(dts_pid, &status, 0);
- if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
- std::cerr << "Child dts process failed" << std::endl;
- exit(1);
- }
- waitpid(dtb_pid, &status, 0);
- if (!WIFEXITED(status) || WEXITSTATUS(status) != 0) {
- std::cerr << "Child dtb process failed" << std::endl;
- exit(1);
- }
-
- return dtb.str();
-}
-
void sim_t::make_dtb()
{
const int reset_vec_size = 8;
0x297, // auipc t0,0x0
0x28593 + (reset_vec_size * 4 << 20), // addi a1, t0, &dtb
0xf1402573, // csrr a0, mhartid
- get_core(0)->xlen == 32 ?
+ get_core(0)->get_xlen() == 32 ?
0x0182a283u : // lw t0,24(t0)
0x0182b283u, // ld t0,24(t0)
0x28067, // jr t0
std::vector<char> rom((char*)reset_vec, (char*)reset_vec + sizeof(reset_vec));
- std::stringstream s;
- s << std::dec <<
- "/dts-v1/;\n"
- "\n"
- "/ {\n"
- " #address-cells = <2>;\n"
- " #size-cells = <2>;\n"
- " compatible = \"ucbbar,spike-bare-dev\";\n"
- " model = \"ucbbar,spike-bare\";\n"
- " cpus {\n"
- " #address-cells = <1>;\n"
- " #size-cells = <0>;\n"
- " timebase-frequency = <" << (CPU_HZ/INSNS_PER_RTC_TICK) << ">;\n";
- for (size_t i = 0; i < procs.size(); i++) {
- s << " CPU" << i << ": cpu@" << i << " {\n"
- " device_type = \"cpu\";\n"
- " reg = <" << i << ">;\n"
- " status = \"okay\";\n"
- " compatible = \"riscv\";\n"
- " riscv,isa = \"" << procs[i]->isa_string << "\";\n"
- " mmu-type = \"riscv," << (procs[i]->max_xlen <= 32 ? "sv32" : "sv48") << "\";\n"
- " clock-frequency = <" << CPU_HZ << ">;\n"
- " CPU" << i << "_intc: interrupt-controller {\n"
- " #interrupt-cells = <1>;\n"
- " interrupt-controller;\n"
- " compatible = \"riscv,cpu-intc\";\n"
- " };\n"
- " };\n";
- }
- s << " };\n";
- for (auto& m : mems) {
- s << std::hex <<
- " memory@" << m.first << " {\n"
- " device_type = \"memory\";\n"
- " reg = <0x" << (m.first >> 32) << " 0x" << (m.first & (uint32_t)-1) <<
- " 0x" << (m.second->size() >> 32) << " 0x" << (m.second->size() & (uint32_t)-1) << ">;\n"
- " };\n";
- }
- s << " soc {\n"
- " #address-cells = <2>;\n"
- " #size-cells = <2>;\n"
- " compatible = \"ucbbar,spike-bare-soc\", \"simple-bus\";\n"
- " ranges;\n"
- " clint@" << CLINT_BASE << " {\n"
- " compatible = \"riscv,clint0\";\n"
- " interrupts-extended = <" << std::dec;
- for (size_t i = 0; i < procs.size(); i++)
- s << "&CPU" << i << "_intc 3 &CPU" << i << "_intc 7 ";
- reg_t clintbs = CLINT_BASE;
- reg_t clintsz = CLINT_SIZE;
- s << std::hex << ">;\n"
- " reg = <0x" << (clintbs >> 32) << " 0x" << (clintbs & (uint32_t)-1) <<
- " 0x" << (clintsz >> 32) << " 0x" << (clintsz & (uint32_t)-1) << ">;\n"
- " };\n"
- " };\n"
- " htif {\n"
- " compatible = \"ucb,htif0\";\n"
- " };\n"
- "};\n";
-
- dts = s.str();
+ dts = make_dts(INSNS_PER_RTC_TICK, CPU_HZ, procs, mems);
std::string dtb = dts_compile(dts);
rom.insert(rom.end(), dtb.begin(), dtb.end());
void sim_t::reset()
{
- make_dtb();
+ if (dtb_enabled)
+ make_dtb();
}
void sim_t::idle()
memcpy(&data, src, sizeof data);
debug_mmu->store_uint64(taddr, data);
}
+
+void sim_t::proc_reset(unsigned id)
+{
+ debug_module.proc_reset(id);
+}
projects / riscv-isa-sim.git / blobdiff