ROM -> RAM -> ROM, waiting for debug int.

[riscv-isa-sim.git] / riscv / sim.h

diff --git a/riscv/sim.h b/riscv/sim.h
index dad32ef493234637a3531c1971d57d7cc4aa7aa6..2e7b214fd3a8ec06f8494013e3a0ca778f73de32 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -89,6 +89,11 @@ private:
   reg_t get_mem(const std::vector<std::string>& args);
   reg_t get_pc(const std::vector<std::string>& args);
 
+  // Return a pointer to Debug RAM in spike address space.
+  char *debug_ram() const {
+      return mem + memsz - DEBUG_SIZE + DEBUG_RAM_START - DEBUG_START;
+  }
+
   friend class htif_isasim_t;
   friend class processor_t;
   friend class mmu_t;