soc/integration/csr_bridge: use registered version only when SDRAM is present.

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
old mode 100644 (file)
new mode 100755 (executable)
index 0f84b94..efefa52
--- a/setup.py
+++ b/setup.py
@@ -1,37 +1,53 @@
 #!/usr/bin/env python3
 
-import sys, os
 from setuptools import setup
 from setuptools import find_packages
 
-here = os.path.abspath(os.path.dirname(__file__))
-README = open(os.path.join(here, "README")).read()
-
-required_version = (3, 3)
-if sys.version_info < required_version:
-       raise SystemExit("LiteEth requires python {0} or greater".format(
-               ".".join(map(str, required_version))))
 
 setup(
-       name="liteeth",
-       version="unknown",
-       description="small footprint and configurable Ethernet core",
-       long_description=README,
-       author="Florent Kermarrec",
-       author_email="florent@enjoy-digital.fr",
-       url="http://enjoy-digital.fr",
-       download_url="https://github.com/enjoy-digital/liteeth",
-       packages=find_packages(here),
-       license="GPL",
-       platforms=["Any"],
-       keywords="HDL ASIC FPGA hardware design",
-       classifiers=[
-               "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
-               "Environment :: Console",
-               "Development Status :: Alpha",
-               "Intended Audience :: Developers",
-               "License :: OSI Approved :: GNU General Public License (GPL)",
-               "Operating System :: OS Independent",
-               "Programming Language :: Python",
-       ],
+    name="litex",
+    description="Python SoC/Core builder for building FPGA based systems.",
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    test_suite="test",
+    license="BSD",
+    python_requires="~=3.6",
+    install_requires=[
+        "migen",
+        "pyserial",
+        "requests",
+        "pythondata-software-compiler_rt",
+    ],
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
+    include_package_data=True,
+    platforms=["Any"],
+    keywords="HDL ASIC FPGA hardware design",
+    classifiers=[
+        "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
+        "Environment :: Console",
+        "Development Status :: Alpha",
+        "Intended Audience :: Developers",
+        "License :: OSI Approved :: BSD License",
+        "Operating System :: OS Independent",
+        "Programming Language :: Python",
+    ],
+    entry_points={
+        "console_scripts": [
+            # full names
+            "litex_term=litex.tools.litex_term:main",
+            "litex_server=litex.tools.litex_server:main",
+            "litex_jtag_uart=litex.tools.litex_jtag_uart:main",
+            "litex_crossover_uart=litex.tools.litex_crossover_uart:main",
+            "litex_sim=litex.tools.litex_sim:main",
+            "litex_read_verilog=litex.tools.litex_read_verilog:main",
+            "litex_simple=litex.boards.targets.simple:main",
+            "litex_json2dts=litex.tools.litex_json2dts:main",
+            # short names
+            "lxterm=litex.tools.litex_term:main",
+            "lxserver=litex.tools.litex_server:main",
+            "lxsim=litex.tools.litex_sim:main",
+        ],
+    },
 )