soc/integration/csr_bridge: use registered version only when SDRAM is present.

[litex.git] / setup.py

diff --git a/setup.py b/setup.py
index fb139718de23a4d5161a6864c9fcf10404ba14dd..efefa52a4a085eed97c1b0812e2b5ae6a0be0228 100755 (executable)
--- a/setup.py
+++ b/setup.py
@@ -1,35 +1,53 @@
 #!/usr/bin/env python3
 
-import sys
 from setuptools import setup
 from setuptools import find_packages
 
 
-if sys.version_info[:3] < (3, 3):
-    raise SystemExit("You need Python 3.3+")
-
-
 setup(
-    name="migen",
-    version="1.0",
-    description="Python toolbox for building complex digital hardware",
-    long_description=open("README.rst").read(),
-    author="Sebastien Bourdeauducq",
-    author_email="sb@m-labs.hk",
-    url="http://m-labs.hk",
-    download_url="https://github.com/m-labs/migen",
-    packages=find_packages(),
-    test_suite="migen.test",
+    name="litex",
+    description="Python SoC/Core builder for building FPGA based systems.",
+    author="Florent Kermarrec",
+    author_email="florent@enjoy-digital.fr",
+    url="http://enjoy-digital.fr",
+    download_url="https://github.com/enjoy-digital/litex",
+    test_suite="test",
     license="BSD",
+    python_requires="~=3.6",
+    install_requires=[
+        "migen",
+        "pyserial",
+        "requests",
+        "pythondata-software-compiler_rt",
+    ],
+    packages=find_packages(exclude=("test*", "sim*", "doc*")),
+    include_package_data=True,
     platforms=["Any"],
     keywords="HDL ASIC FPGA hardware design",
     classifiers=[
         "Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
         "Environment :: Console",
-        "Development Status :: Beta",
+        "Development Status :: Alpha",
         "Intended Audience :: Developers",
         "License :: OSI Approved :: BSD License",
         "Operating System :: OS Independent",
         "Programming Language :: Python",
     ],
+    entry_points={
+        "console_scripts": [
+            # full names
+            "litex_term=litex.tools.litex_term:main",
+            "litex_server=litex.tools.litex_server:main",
+            "litex_jtag_uart=litex.tools.litex_jtag_uart:main",
+            "litex_crossover_uart=litex.tools.litex_crossover_uart:main",
+            "litex_sim=litex.tools.litex_sim:main",
+            "litex_read_verilog=litex.tools.litex_read_verilog:main",
+            "litex_simple=litex.boards.targets.simple:main",
+            "litex_json2dts=litex.tools.litex_json2dts:main",
+            # short names
+            "lxterm=litex.tools.litex_term:main",
+            "lxserver=litex.tools.litex_server:main",
+            "lxsim=litex.tools.litex_sim:main",
+        ],
+    },
 )