only add pc_i in DMI mode

[libresoc-litex.git] / sim.py

diff --git a/sim.py b/sim.py
index 550339e46a22169fe19510da5d3032202f3f8aec..accac4fabc3196f3f39c0c1f3caf396953f69a69 100755 (executable)
--- a/sim.py
+++ b/sim.py
@@ -64,7 +64,9 @@ class LibreSoCSim(SoCSDRAM):
         #            "tests/decrementer/decrementer.bin"
         #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
         #            "hello_world/hello_world.bin"
-        ram_fname = None
+        ram_fname = "/home/lkcl/src/libresoc/microwatt/" \
+                    "tests/mmu/mmu.bin"
+        #ram_fname = None
 
         # reserve XICS ICP and XICS memory addresses.
         self.mem_map['xicsicp'] = 0xc0004000