ls2: add support for the Nexys Video board

[ls2.git] / simsoc.ys

diff --git a/simsoc.ys b/simsoc.ys
index 0e2c880b8f9331ef20d522309984dde72a429fa2..a4adcefdcd7103aa29cc6578bdaf470b89e0f845 100644 (file)
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -1,4 +1,15 @@
+# rad the main peripheral fabric, then uart16550, and finally libresoc core
+# we do not have to do include the micron ddr3 model or the lattice ecp5
+# models because apparently they're good to go, already (icarus is a lot
+# stricter than verilator, hence the munging below)
+
+# peripheral fabric
 read_ilang build_simsoc/top.il
+
+# main core (any core, it's all good)
+read_verilog  ./external_core_top.v
+
+# UART 16550
 read_verilog  ../uart16550/rtl/verilog/raminfr.v
 read_verilog  ../uart16550/rtl/verilog/uart_defines.v
 read_verilog  ../uart16550/rtl/verilog/uart_rfifo.v
@@ -11,12 +22,50 @@ read_verilog  ../uart16550/rtl/verilog/uart_transmitter.v
 read_verilog  ../uart16550/rtl/verilog/uart_receiver.v
 read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
-read_verilog  ./external_core_top.v
 
+# Tercel QSPI
+read_verilog  ../tercel-qspi/tercel/phy.v 
+read_verilog  ../tercel-qspi/tercel/wishbone_spi_master.v
+
+# WB Async Bridge
+read_verilog  ../verilog-wishbone/rtl/wb_async_reg.v 
+
+# errors in the ethmac rtl, comment out for now
+#read_verilog  ../ethmac/rtl/verilog/eth_clockgen.v
+#read_verilog  ../ethmac/rtl/verilog/eth_cop.v
+#read_verilog  ../ethmac/rtl/verilog/eth_crc.v
+#read_verilog  ../ethmac/rtl/verilog/eth_fifo.v
+#read_verilog  ../ethmac/rtl/verilog/eth_maccontrol.v
+#read_verilog  ../ethmac/rtl/verilog/ethmac_defines.v
+#read_verilog  ../ethmac/rtl/verilog/eth_macstatus.v
+#read_verilog  ../ethmac/rtl/verilog/ethmac.v
+#read_verilog  ../ethmac/rtl/verilog/eth_miim.v
+#read_verilog  ../ethmac/rtl/verilog/eth_outputcontrol.v
+#read_verilog  ../ethmac/rtl/verilog/eth_random.v
+#read_verilog  ../ethmac/rtl/verilog/eth_receivecontrol.v
+#read_verilog  ../ethmac/rtl/verilog/eth_registers.v
+#read_verilog  ../ethmac/rtl/verilog/eth_register.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxaddrcheck.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxcounters.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxethmac.v
+#read_verilog  ../ethmac/rtl/verilog/eth_rxstatem.v
+#read_verilog  ../ethmac/rtl/verilog/eth_shiftreg.v
+#read_verilog  ../ethmac/rtl/verilog/eth_spram_256x32.v
+#read_verilog  ../ethmac/rtl/verilog/eth_top.v
+#read_verilog  ../ethmac/rtl/verilog/eth_transmitcontrol.v
+#read_verilog  ../ethmac/rtl/verilog/eth_txcounters.v
+#read_verilog  ../ethmac/rtl/verilog/eth_txethmac.v
+#read_verilog  ../ethmac/rtl/verilog/eth_txstatem.v
+#read_verilog  ../ethmac/rtl/verilog/eth_wishbone.v
+#read_verilog  ../ethmac/rtl/verilog/timescale.v
+
+# stop yosys deleting stuff
 setattr -mod -set keep 1 uart_transmitter
 setattr -mod -set keep 1 uart_receiver
 
 delete w:$verilog_initial_trigger
+
+# these are most of "proc"
 proc_prune
 proc_clean
 proc_rmdead
@@ -29,8 +78,11 @@ proc_rmdead
 proc_memwr
 proc_clean
 opt_expr -keepdc
+
+# these are important to do in this order
 memory_collect
 pmuxtree
+
 #opt_mem
 #opt_mem_priority
 #opt_mem_feedback