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[riscv-isa-sim.git] / softfloat / f64_classify.c

diff --git a/softfloat/f64_classify.c b/softfloat/f64_classify.c
index 2ec124b8acb4a5de648e32a233f1230815e9c31c..180abde3cb1d5919420e3859f7fd88ab6f20404a 100755 (executable)
--- a/softfloat/f64_classify.c
+++ b/softfloat/f64_classify.c
@@ -17,17 +17,20 @@ uint_fast16_t f64_classify( float64_t a )
     uint_fast16_t infOrNaN = expF64UI( uiA ) == 0x7FF;
     uint_fast16_t subnormalOrZero = expF64UI( uiA ) == 0;
     bool sign = signF64UI( uiA );
+    bool fracZero = fracF64UI( uiA ) == 0;
+    bool isNaN = isNaNF64UI( uiA );
+    bool isSNaN = softfloat_isSigNaNF64UI( uiA );
 
     return
-        (  sign && infOrNaN && fracF64UI( uiA ) == 0 )          << 0 |
-        (  sign && !infOrNaN && !subnormalOrZero )              << 1 |
-        (  sign && subnormalOrZero && fracF64UI( uiA ) )        << 2 |
-        (  sign && subnormalOrZero && fracF64UI( uiA ) == 0 )   << 3 |
-        ( !sign && infOrNaN && fracF64UI( uiA ) == 0 )          << 7 |
-        ( !sign && !infOrNaN && !subnormalOrZero )              << 6 |
-        ( !sign && subnormalOrZero && fracF64UI( uiA ) )        << 5 |
-        ( !sign && subnormalOrZero && fracF64UI( uiA ) == 0 )   << 4 |
-        ( isNaNF64UI( uiA ) &&  softfloat_isSigNaNF64UI( uiA )) << 8 |
-        ( isNaNF64UI( uiA ) && !softfloat_isSigNaNF64UI( uiA )) << 9;
+        (  sign && infOrNaN && fracZero )          << 0 |
+        (  sign && !infOrNaN && !subnormalOrZero ) << 1 |
+        (  sign && subnormalOrZero && !fracZero )  << 2 |
+        (  sign && subnormalOrZero && fracZero )   << 3 |
+        ( !sign && infOrNaN && fracZero )          << 7 |
+        ( !sign && !infOrNaN && !subnormalOrZero ) << 6 |
+        ( !sign && subnormalOrZero && !fracZero )  << 5 |
+        ( !sign && subnormalOrZero && fracZero )   << 4 |
+        ( isNaN &&  isSNaN )                       << 8 |
+        ( isNaN && !isSNaN )                       << 9;
 }