update comments

[ieee754fpu.git] / src / add / example_buf_pipe.py

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 7950e3ea437e6e24a76d1f0015aa1e260a7452a9..4bb7cdf1e87fe6f929c7b17342df71924e467af8 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -1,9 +1,11 @@
 """ Pipeline and BufferedHandshake examples
 """
 
+from nmoperator import eq
+from iocontrol import (PrevControl, NextControl)
 from singlepipe import (PrevControl, NextControl, ControlBase,
                         StageCls, Stage, StageChain,
-                        BufferedHandshake, UnbufferedPipeline, eq)
+                        BufferedHandshake, UnbufferedPipeline)
 
 from nmigen import Signal, Module
 from nmigen.cli import verilog, rtlil