add 2 stage buffered pipeline unit test, reduce to 16-bit to make vcd clearer

[ieee754fpu.git] / src / add / example_buf_pipe.py

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 6db85fc4e7e4ccedf8967cf6eb6be00077222c75..5faee7876c83e602fecb47e6c9ba366a7ec7aa90 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -40,7 +40,6 @@
 """
 
 from nmigen import Signal, Cat, Const, Mux, Module
-from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
 class BufPipe:
@@ -59,16 +58,16 @@ class BufPipe:
         #self.i_p_rst = Signal()    # >>in - comes in from PREVIOUS stage
         self.i_p_stb = Signal()    # >>in - comes in from PREVIOUS stage
         self.i_n_busy = Signal()   # in<< - comes in from the NEXT stage
-        self.i_data = Signal(32) # >>in - comes in from the PREVIOUS stage
+        self.i_data = Signal(16) # >>in - comes in from the PREVIOUS stage
         #self.i_rst = Signal()
 
         # buffered
-        self.r_data = Signal(32)
+        self.r_data = Signal(16)
 
         # output
         self.o_n_stb = Signal()    # out>> - goes out to the NEXT stage
         self.o_p_busy = Signal()   # <<out - goes out to the PREVIOUS stage
-        self.o_data = Signal(32) # out>> - goes out to the NEXT stage
+        self.o_data = Signal(16) # out>> - goes out to the NEXT stage
 
     def pre_process(self, d_in):
         return d_in | 0xf0000
@@ -91,8 +90,9 @@ class BufPipe:
         ]
 
         # store result of processing in combinatorial temporary
-        result = Signal(32)
-        m.d.comb += result.eq(self.process(self.i_data))
+        result = Signal(16)
+        with m.If(self.i_p_stb): # input is valid: process it
+            m.d.comb += result.eq(self.process(self.i_data))
         with m.If(o_p_busyn): # not stalled
             m.d.sync += self.r_data.eq(result)
 
@@ -140,39 +140,9 @@ class BufPipe:
                ]
 
 
-def testbench(dut):
-    #yield dut.i_p_rst.eq(1)
-    yield dut.i_n_busy.eq(1)
-    yield dut.o_p_busy.eq(1)
-    yield
-    yield
-    #yield dut.i_p_rst.eq(0)
-    yield dut.i_n_busy.eq(0)
-    yield dut.i_data.eq(5)
-    yield dut.i_p_stb.eq(1)
-    yield
-    yield dut.i_data.eq(7)
-    yield
-    yield dut.i_data.eq(2)
-    yield
-    yield dut.i_n_busy.eq(1)
-    yield dut.i_data.eq(9)
-    yield
-    yield dut.i_p_stb.eq(0)
-    yield dut.i_data.eq(12)
-    yield
-    yield dut.i_data.eq(32)
-    yield dut.i_n_busy.eq(0)
-    yield
-    yield
-    yield
-    yield
-
-
 if __name__ == '__main__':
     dut = BufPipe()
     vl = rtlil.convert(dut, ports=dut.ports())
     with open("test_bufpipe.il", "w") as f:
         f.write(vl)
-    run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")