add a couple of example names to one of the pipeline stages

[ieee754fpu.git] / src / add / example_buf_pipe.py

diff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py
index 6d13099b93dc549b03598a43cb13cbc876681715..a91b50842393ac38d7d02400eff258541e0f633a 100644 (file)
--- a/src/add/example_buf_pipe.py
+++ b/src/add/example_buf_pipe.py
@@ -72,6 +72,14 @@ class PrevControl:
                 eq(self.i_data, prev.i_data),
                ]
 
+    def i_valid_logic(self):
+        vlen = len(self.i_valid)
+        if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
+            all1s = Const(-1, (len(self.i_valid), False))
+            return self.i_valid == all1s
+        # single-bit i_valid case
+        return self.i_valid
+
 
 class NextControl:
     """ contains the signals that go *to* the next stage (both in and out)
@@ -104,8 +112,8 @@ class NextControl:
 
 def eq(o, i):
     """ makes signals equal: a helper routine which identifies if it is being
-        passsed a list (or tuple) of objects, and calls the objects' eq
-        function.
+        passed a list (or tuple) of objects, or signals, or Records, and calls
+        the objects' eq function.
 
         complex objects (classes) can be used: they must follow the
         convention of having an eq member function, which takes the
@@ -130,7 +138,10 @@ def eq(o, i):
                     rres = eq(ao.fields[field_name], ai[field_name])
                 res += rres
         else:
-            res.append(ao.eq(ai))
+            rres = ao.eq(ai)
+            if not isinstance(rres, Sequence):
+                rres = [rres]
+            res += rres
     return res
 
 
@@ -227,16 +238,11 @@ class BufferedPipeline(PipelineBase):
             self.stage.setup(m, self.p.i_data)
 
         # establish some combinatorial temporaries
-        p_i_valid = Signal(reset_less=True)
         o_n_validn = Signal(reset_less=True)
         i_p_valid_o_p_ready = Signal(reset_less=True)
-        vlen = len(self.p.i_valid)
-        if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
-            all1s = Const(-1, (len(self.p.i_valid), False))
-            m.d.comb += p_i_valid.eq(self.p.i_valid == all1s)
-        else: # single-bit i_valid case
-            m.d.comb += p_i_valid.eq(self.p.i_valid)
-        m.d.comb += [ o_n_validn.eq(~self.n.o_valid),
+        p_i_valid = Signal(reset_less=True)
+        m.d.comb += [p_i_valid.eq(self.p.i_valid_logic()),
+                     o_n_validn.eq(~self.n.o_valid),
                      i_p_valid_o_p_ready.eq(p_i_valid & self.p.o_ready),
         ]
 
@@ -316,10 +322,10 @@ class ExampleStage:
     """
 
     def ispec():
-        return Signal(16)
+        return Signal(16, name="example_input_signal")
 
     def ospec():
-        return Signal(16)
+        return Signal(16, name="example_output_signal")
 
     def process(i):
         """ process the input data and returns it (adds 1)
@@ -367,10 +373,12 @@ class CombPipe(PipelineBase):
         if hasattr(self.stage, "setup"):
             self.stage.setup(m, r_data)
 
+        p_i_valid = Signal(reset_less=True)
+        m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
         m.d.comb += eq(result, self.stage.process(r_data))
         m.d.comb += self.n.o_valid.eq(self._data_valid)
         m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready)
-        m.d.sync += self._data_valid.eq(self.p.i_valid | \
+        m.d.sync += self._data_valid.eq(p_i_valid | \
                                         (~self.n.i_ready & self._data_valid))
         with m.If(self.p.i_valid & self.p.o_ready):
             m.d.sync += eq(r_data, self.p.i_data)