convert to more general base classes, start support for FP64

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 3b60567144c5f431f9ac9e3d682c672a4ecf76e1..7d98eb6be8c53e1e0b2967a60b4dce04057384fc 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -22,7 +22,7 @@ class FPMUL(FPBase):
         # Latches
         a = FPNum(self.width)
         b = FPNum(self.width)
-        z = FPNum(self.width, 24)
+        z = FPNum(self.width, False)
 
         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
 
@@ -259,4 +259,4 @@ always @(posedge clk)
       s_output_z_stb <= 0;
     end
  end
- """
\ No newline at end of file
+ """