Translated more of the special cases to nmigen

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index 3ad6ac4e2582cd5a4de5a885267d5992aa32ac33..ba24e078138f937d7da1acb21c58bad7953e17e8 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -76,6 +76,13 @@ class FPMUL(FPBase):
                        with m.Elif(b.is_inf()):
                                m.next += "put_z"
                                m.d.sync += z.inf(0)
+                       #if a is zero return NaN
+                       with m.If(a.is_zero()):
+                               m.next += "put_z"
+                               m.d.sync += z.nan(1)
+                       with m.Elif(a.is_zero()):
+                               m.next += "put_z"
+                               m.d.sync += z.zero(0)