whoops, self.width not self.m_width

[ieee754fpu.git] / src / add / fmul.py

diff --git a/src/add/fmul.py b/src/add/fmul.py
index c5e3f9d253fc2a43382e597e30a786ef4d98fa4f..deb9ffff803c2c0fc64afa6b01acf245ace196b0 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -24,7 +24,7 @@ class FPMUL(FPBase):
         b = FPNum(self.width, False)
         z = FPNum(self.width, False)
 
-        mw = (self.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
+        mw = (self.width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
         product = Signal(mw)
 
         of = Overflow()