update comments

[ieee754fpu.git] / src / add / fpbase.py

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index c53cabbba555e2fd486acd62ba9106dffe36314c..f49085921d914d600dea950d3707ab924eb0272b 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -2,7 +2,7 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Signal, Cat, Const, Mux, Module
+from nmigen import Signal, Cat, Const, Mux, Module, Elaboratable
 from math import log
 from operator import or_
 from functools import reduce
@@ -60,7 +60,7 @@ class MultiShift:
         return res
 
 
-class FPNumBase:
+class FPNumBase: #(Elaboratable):
     """ Floating-point Base Number Class
     """
     def __init__(self, width, m_extra=True):
@@ -145,6 +145,11 @@ class FPNumBase:
     def _is_denormalised(self):
         return (self.exp_n126) & (self.m_msbzero)
 
+    def __iter__(self):
+        yield self.s
+        yield self.e
+        yield self.m
+
     def eq(self, inp):
         return [self.s.eq(inp.s), self.e.eq(inp.e), self.m.eq(inp.m)]
 
@@ -209,7 +214,7 @@ class FPNumOut(FPNumBase):
         return self.create2(s, self.N127, self.mzero)
 
 
-class MultiShiftRMerge:
+class MultiShiftRMerge(Elaboratable):
     """ shifts down (right) and merges lower bits into m[0].
         m[0] is the "sticky" bit, basically
     """
@@ -252,7 +257,7 @@ class MultiShiftRMerge:
         return m
 
 
-class FPNumShift(FPNumBase):
+class FPNumShift(FPNumBase, Elaboratable):
     """ Floating-point Number Class for shifting
     """
     def __init__(self, mainm, op, inv, width, m_extra=True):
@@ -459,7 +464,7 @@ class FPNumIn(FPNumBase):
                 self.m.eq(sm.lshift(self.m, maxslen))
                ]
 
-class Trigger:
+class Trigger(Elaboratable):
     def __init__(self):
 
         self.stb = Signal(reset=0)
@@ -484,8 +489,10 @@ class FPOpIn(PrevControl):
     def __init__(self, width):
         PrevControl.__init__(self)
         self.width = width
-        self.v = Signal(width)
-        self.i_data = self.v
+
+    @property
+    def v(self):
+        return self.data_i
 
     def chain_inv(self, in_op, extra=None):
         stb = in_op.stb
@@ -510,8 +517,10 @@ class FPOpOut(NextControl):
     def __init__(self, width):
         NextControl.__init__(self)
         self.width = width
-        self.v = Signal(width)
-        self.o_data = self.v
+
+    @property
+    def v(self):
+        return self.data_o
 
     def chain_inv(self, in_op, extra=None):
         stb = in_op.stb
@@ -532,7 +541,7 @@ class FPOpOut(NextControl):
                ]
 
 
-class Overflow:
+class Overflow: #(Elaboratable):
     def __init__(self):
         self.guard = Signal(reset_less=True)     # tot[2]
         self.round_bit = Signal(reset_less=True) # tot[1]
@@ -541,6 +550,12 @@ class Overflow:
 
         self.roundz = Signal(reset_less=True)
 
+    def __iter__(self):
+        yield self.guard
+        yield self.round_bit
+        yield self.sticky
+        yield self.m0
+
     def eq(self, inp):
         return [self.guard.eq(inp.guard),
                 self.round_bit.eq(inp.round_bit),
@@ -569,7 +584,7 @@ class FPBase:
         """
         res = v.decode2(m)
         ack = Signal()
-        with m.If((op.o_ready) & (op.i_valid_test)):
+        with m.If((op.ready_o) & (op.valid_i_test)):
             m.next = next_state
             # op is latched in from FPNumIn class on same ack/stb
             m.d.comb += ack.eq(0)
@@ -679,11 +694,11 @@ class FPBase:
         m.d.sync += [
           out_z.v.eq(z.v)
         ]
-        with m.If(out_z.o_valid & out_z.i_ready_test):
-            m.d.sync += out_z.o_valid.eq(0)
+        with m.If(out_z.valid_o & out_z.ready_i_test):
+            m.d.sync += out_z.valid_o.eq(0)
             m.next = next_state
         with m.Else():
-            m.d.sync += out_z.o_valid.eq(1)
+            m.d.sync += out_z.valid_o.eq(1)
 
 
 class FPState(FPBase):