update comments

[ieee754fpu.git] / src / add / fpcommon / putz.py

diff --git a/src/add/fpcommon/putz.py b/src/add/fpcommon/putz.py
index e1b73d62525801cb3a52214e73dbd35931e1197d..8173ed859befe0d5adbad6820d98789325e2b6a4 100644 (file)
--- a/src/add/fpcommon/putz.py
+++ b/src/add/fpcommon/putz.py
@@ -2,28 +2,9 @@
 # Copyright (C) Jonathan P Dawson 2013
 # 2013-12-12
 
-from nmigen import Module, Signal, Cat, Mux, Array, Const
-from nmigen.lib.coding import PriorityEncoder
+from nmigen import Signal
 from nmigen.cli import main, verilog
-from math import log
-
-from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
-from fpbase import MultiShiftRMerge, Trigger
-from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
-                        PassThroughStage)
-from multipipe import CombMuxOutPipe
-from multipipe import PriorityCombMuxInPipe
-
-from fpbase import FPState, FPID
-from fpcommon.getop import (FPGetOpMod, FPGetOp, FPNumBase2Ops, FPADDBaseData,                              FPGet2OpMod, FPGet2Op)
-from fpcommon.denorm import (FPSCData, FPAddDeNormMod, FPAddDeNorm)
-from fpcommon.postcalc import FPAddStage1Data
-from fpcommon.postnormalise import (FPNorm1Data, FPNorm1ModSingle,
-                            FPNorm1ModMulti, FPNorm1Single, FPNorm1Multi)
-from fpcommon.roundz import (FPRoundData, FPRoundMod, FPRound)
-from fpcommon.corrections import (FPCorrectionsMod, FPCorrections)
-from fpcommon.pack import (FPPackData, FPPackMod, FPPack)
-from fpcommon.normtopack import FPNormToPack
+from fpbase import FPState
 
 
 class FPPutZ(FPState):
@@ -44,11 +25,11 @@ class FPPutZ(FPState):
         m.d.sync += [
           self.out_z.z.v.eq(self.in_z)
         ]
-        with m.If(self.out_z.z.stb & self.out_z.z.ack):
-            m.d.sync += self.out_z.z.stb.eq(0)
+        with m.If(self.out_z.z.valid_o & self.out_z.z.ready_i_test):
+            m.d.sync += self.out_z.z.valid_o.eq(0)
             m.next = self.to_state
         with m.Else():
-            m.d.sync += self.out_z.z.stb.eq(1)
+            m.d.sync += self.out_z.z.valid_o.eq(1)
 
 
 class FPPutZIdx(FPState):
@@ -65,15 +46,15 @@ class FPPutZIdx(FPState):
     def action(self, m):
         outz_stb = Signal(reset_less=True)
         outz_ack = Signal(reset_less=True)
-        m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
-                     outz_ack.eq(self.out_zs[self.in_mid].ack),
+        m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].valid_o),
+                     outz_ack.eq(self.out_zs[self.in_mid].ready_i_test),
                     ]
         m.d.sync += [
           self.out_zs[self.in_mid].v.eq(self.in_z.v)
         ]
         with m.If(outz_stb & outz_ack):
-            m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
+            m.d.sync += self.out_zs[self.in_mid].valid_o.eq(0)
             m.next = self.to_state
         with m.Else():
-            m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
+            m.d.sync += self.out_zs[self.in_mid].valid_o.eq(1)