latch into FPNumIn within module

[ieee754fpu.git] / src / add / nmigen_add_experiment.py

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index b1e633ebf79286952346a18aa49ec685ad563396..184aa91ee03216985254c2c1e1d2a6ab14d31955 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -25,14 +25,17 @@ class FPADD(FPBase):
         m = Module()
 
         # Latches
-        a = FPNumIn(self.width)
-        b = FPNumIn(self.width)
+        a = FPNumIn(self.in_a, self.width)
+        b = FPNumIn(self.in_b, self.width)
         z = FPNumOut(self.width, False)
 
         m.submodules.fpnum_a = a
         m.submodules.fpnum_b = b
         m.submodules.fpnum_z = z
 
+        m.d.comb += a.v.eq(self.in_a.v)
+        m.d.comb += b.v.eq(self.in_b.v)
+
         w = z.m_width + 4
         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow