from nmigen.compat.fhdl.bitcontainer import value_bits_sign
from contextlib import contextmanager
-from singlepipe import eq, StageCls, ControlBase, BufferedPipeline
+from nmoperator import eq
+from singlepipe import StageCls, ControlBase, BufferedHandshake
from singlepipe import UnbufferedPipeline
class ObjectProxy:
- def __init__(self, m, name=None, pipemode=False):
+ def __init__(self, m, name=None, pipemode=False, syncmode=True):
self._m = m
if name is None:
name = tracer.get_var_name(default=None)
self.name = name
self._pipemode = pipemode
+ self._syncmode = syncmode
self._eqs = {}
self._assigns = []
self._preg_map = {}
self._preg_map[name] = new_pipereg
#object.__setattr__(self, name, new_pipereg)
if self._pipemode:
- print ("OP pipemode", new_pipereg, value)
- #self._m.d.comb += eq(new_pipereg, value)
- pass
+ #print ("OP pipemode", self._syncmode, new_pipereg, value)
+ assign = eq(new_pipereg, value)
+ if self._syncmode:
+ self._m.d.sync += assign
+ else:
+ self._m.d.comb += assign
elif self._m:
- print ("OP !pipemode assign", new_pipereg, value, type(value))
+ #print ("OP !pipemode assign", new_pipereg, value, type(value))
self._m.d.comb += eq(new_pipereg, value)
else:
- print ("OP !pipemode !m", new_pipereg, value, type(value))
+ #print ("OP !pipemode !m", new_pipereg, value, type(value))
self._assigns += eq(new_pipereg, value)
if isinstance(value, ObjectProxy):
- print ("OP, defer assigns:", value._assigns)
+ #print ("OP, defer assigns:", value._assigns)
self._assigns += value._assigns
self._eqs.append(value._eqs)
for s in self.stages:
print ("stage specs", s, s.inspecs, s.outspecs)
if self.pipetype == 'buffered':
- p = BufferedPipeline(s)
+ p = BufferedHandshake(s)
else:
p = AutoPipe(s, s.assigns)
pipes.append(p)