update comments

[ieee754fpu.git] / src / add / record_experiment.py

diff --git a/src/add/record_experiment.py b/src/add/record_experiment.py
index 4dbe817a6f7e879646585ae694115e109017f0d0..1789c3bd8a6125819153921da42dcf9f6b87a14f 100644 (file)
--- a/src/add/record_experiment.py
+++ b/src/add/record_experiment.py
@@ -1,9 +1,9 @@
-from nmigen import Module, Signal, Mux, Const
+from nmigen import Module, Signal, Mux, Const, Elaboratable
 from nmigen.hdl.rec import Record, Layout, DIR_NONE
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen.compat.fhdl.bitcontainer import value_bits_sign
-from singlepipe import flatten, RecordObject
+from singlepipe import cat, RecordObject
 
 
 class RecordTest:
@@ -28,7 +28,7 @@ class RecordTest:
         print (self.r1.fields)
         print (self.r1.shape())
         print ("width", len(self.r1))
-        m.d.comb += self.sig123.eq(flatten(self.r1))
+        m.d.comb += self.sig123.eq(cat(self.r1))
 
         return m
 
@@ -51,7 +51,7 @@ def testbench(dut):
 
 
 
-class RecordTest2:
+class RecordTest2(Elaboratable):
 
     def __init__(self):
         self.r1 = RecordObject()
@@ -65,7 +65,7 @@ class RecordTest2:
     def elaborate(self, platform):
         m = Module()
 
-        m.d.comb += flatten(self.r1).eq(self.sig123)
+        m.d.comb += cat(self.r1).eq(self.sig123)
 
         return m