still transmit data if ready

[ieee754fpu.git] / src / add / singlepipe.py

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index d7f0972d7b1b6a37b3ba0842a5c118f8c99681ad..248a5f6e62386c4a190ad116ac2650320bc77fd8 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -705,8 +705,9 @@ class BufferedPipeline2(ControlBase):
                                  ]
         # previous invalid or not ready, however next is accepting
         with self.m.Elif(n_i_ready):
+            self.m.d.sync += [ eq(self.n.o_data, result)]
             # TODO: could still send data here (if there was any)
-            self.m.d.sync += self.n.o_valid.eq(0), # ...so set output invalid
+            self.m.d.sync += self.n.o_valid.eq(0) # ...so set output invalid
 
         # if next is ready, so is previous
         self.m.d.comb += self.p._o_ready.eq(n_i_ready)