simplify UnbufferedPipeline2

[ieee754fpu.git] / src / add / singlepipe.py

diff --git a/src/add/singlepipe.py b/src/add/singlepipe.py
index bb1426a038610dfb107c8a4e42ec8347f49cfe3d..c10b34e9a7c9b42b8f7012fd3eeda964bb135ea2 100644 (file)
--- a/src/add/singlepipe.py
+++ b/src/add/singlepipe.py
@@ -845,8 +845,7 @@ class UnbufferedPipeline2(ControlBase):
 
         self.m.d.comb += self.n.o_valid.eq(buf_full | p_i_valid)
         self.m.d.comb += self.p._o_ready.eq(~buf_full)
-        self.m.d.sync += buf_full.eq(~self.n.i_ready_test & \
-                                        (p_i_valid | buf_full))
+        self.m.d.sync += buf_full.eq(~self.n.i_ready_test & self.n.o_valid)
 
         odata = Mux(buf_full, buf, self.stage.process(self.p.i_data))
         self.m.d.comb += eq(self.n.o_data, odata)