add stage_ctl argument to PrevControl / NextControl on pipeline

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 3f3cce2190a971b2e56dd8b3cbc4ba3a88827bcf..2376f337dcdd3a825642b4178816cc90f17454e2 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -594,8 +594,11 @@ class ExampleStageDelayCls(StageCls):
     def ospec(self):
         return Signal(16, name="example_output_signal")
 
-    def data_ready(self, i):
-        pass
+    def p_o_ready(self, m, p_in, p_out):
+        m.d.comb += p_out.eq(p_in)
+
+    def n_o_valid(self, m, n_in, n_out):
+        m.d.comb += n_out.eq(n_in)
 
     def process(self, i):
         """ process the input data and returns it (adds 1)