update comments

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 1408164a02647ccdfabc35db1cdca056367c6306..37f2b31f8b0a3ce38d2067b569a28344e6ab7fd9 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -635,8 +635,8 @@ class ExampleStageDelayCls(StageCls, Elaboratable):
 class ExampleBufDelayedPipe(BufferedHandshake):
 
     def __init__(self):
-        self.stage = ExampleStageDelayCls(valid_trigger=2)
-        BufferedHandshake.__init__(self, self.stage, stage_ctl=True)
+        stage = ExampleStageDelayCls(valid_trigger=2)
+        BufferedHandshake.__init__(self, stage, stage_ctl=True)
 
     def elaborate(self, platform):
         m = BufferedHandshake.elaborate(self, platform)
@@ -667,8 +667,8 @@ def resultfn_12(data_o, expected, i, o):
 class ExampleUnBufDelayedPipe(BufferedHandshake):
 
     def __init__(self):
-        self.stage = ExampleStageDelayCls(valid_trigger=3)
-        BufferedHandshake.__init__(self, self.stage, stage_ctl=True)
+        stage = ExampleStageDelayCls(valid_trigger=3)
+        BufferedHandshake.__init__(self, stage, stage_ctl=True)
 
     def elaborate(self, platform):
         m = BufferedHandshake.elaborate(self, platform)
@@ -790,12 +790,14 @@ class ExampleFIFOPassThruPipe1(ControlBase):
         m = ControlBase.elaborate(self, platform)
 
         pipe1 = FIFOTest16()
-        pipe2 = ExamplePassAdd1Pipe()
+        pipe2 = FIFOTest16()
+        pipe3 = ExamplePassAdd1Pipe()
 
         m.submodules.pipe1 = pipe1
         m.submodules.pipe2 = pipe2
+        m.submodules.pipe3 = pipe3
 
-        m.d.comb += self.connect([pipe1, pipe2])
+        m.d.comb += self.connect([pipe1, pipe2, pipe3])
 
         return m