pass in flatten/processing function into _connect_in/out

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index 3a15ab6de2c0c4276d921123bc2ef92d0a6f28fb..6bf690c24e81703afd1fa11b47f160f3172a7b2f 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -28,6 +28,7 @@ from singlepipe import UnbufferedPipeline2
 from singlepipe import SimpleHandshake
 from singlepipe import PassThroughHandshake
 from singlepipe import PassThroughStage
+from singlepipe import FIFOtest
 
 from random import randint, seed
 
@@ -758,6 +759,40 @@ class ExampleBufPassThruPipe(ControlBase):
         return m
 
 
+######################################################################
+# Test 20
+######################################################################
+
+def iospecfn():
+    return Signal(16, name="din")
+
+class FIFOTest16(FIFOtest):
+
+
+    def __init__(self):
+        FIFOtest.__init__(self, iospecfn, 16, 2)
+
+
+######################################################################
+# Test 21
+######################################################################
+
+class ExampleFIFOPassThruPipe1(ControlBase):
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        pipe1 = FIFOTest16()
+        pipe2 = ExamplePassAdd1Pipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+
 ######################################################################
 # Test 997
 ######################################################################
@@ -849,7 +884,7 @@ class ExampleBufUnBufPipe(ControlBase):
 # Unit Tests
 ######################################################################
 
-num_tests = 100
+num_tests = 10
 
 if __name__ == '__main__':
     print ("test 1")
@@ -1031,6 +1066,30 @@ if __name__ == '__main__':
     with open("test_bufpass19.il", "w") as f:
         f.write(vl)
 
+    print ("test 20")
+    dut = FIFOTest16()
+    data = data_chain1()
+    test = Test5(dut, test_identical_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_fifo20.il", "w") as f:
+        f.write(vl)
+
+    print ("test 21")
+    dut = ExampleFIFOPassThruPipe1()
+    data = data_chain1()
+    test = Test5(dut, test12_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_fifopass21.il", "w") as f:
+        f.write(vl)
+
     print ("test 997")
     dut = ExampleBufPassThruPipe2()
     data = data_chain1()