pass in flatten/processing function into _connect_in/out

[ieee754fpu.git] / src / add / test_buf_pipe.py

diff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py
index adb20cbec989feb38af2e8aa842cc45faec35fcc..6bf690c24e81703afd1fa11b47f160f3172a7b2f 100644 (file)
--- a/src/add/test_buf_pipe.py
+++ b/src/add/test_buf_pipe.py
@@ -22,10 +22,13 @@ from nmigen.cli import verilog, rtlil
 from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
 from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
 from example_buf_pipe import ExampleStageCls
-from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
+from example_buf_pipe import PrevControl, NextControl, BufferedHandshake
 from example_buf_pipe import StageChain, ControlBase, StageCls
 from singlepipe import UnbufferedPipeline2
 from singlepipe import SimpleHandshake
+from singlepipe import PassThroughHandshake
+from singlepipe import PassThroughStage
+from singlepipe import FIFOtest
 
 from random import randint, seed
 
@@ -310,14 +313,14 @@ class ExampleBufPipe2(ControlBase):
 # Test 9
 ######################################################################
 
-class ExampleBufPipeChain2(BufferedPipeline):
+class ExampleBufPipeChain2(BufferedHandshake):
     """ connects two stages together as a *single* combinatorial stage.
     """
     def __init__(self):
         stage1 = ExampleStageCls()
         stage2 = ExampleStageCls()
         combined = StageChain([stage1, stage2])
-        BufferedPipeline.__init__(self, combined)
+        BufferedHandshake.__init__(self, combined)
 
 
 def data_chain2():
@@ -408,13 +411,13 @@ class ExampleLTPipeline(UnbufferedPipeline):
         UnbufferedPipeline.__init__(self, stage)
 
 
-class ExampleLTBufferedPipeDerived(BufferedPipeline):
+class ExampleLTBufferedPipeDerived(BufferedHandshake):
     """ an example of how to use the buffered pipeline.
     """
 
     def __init__(self):
         stage = LTStageDerived()
-        BufferedPipeline.__init__(self, stage)
+        BufferedHandshake.__init__(self, stage)
 
 
 def test6_resultfn(o_data, expected, i, o):
@@ -550,13 +553,13 @@ class ExampleAddClassStage(StageCls):
         return i.op1 + i.op2
 
 
-class ExampleBufPipeAddClass(BufferedPipeline):
+class ExampleBufPipeAddClass(BufferedHandshake):
     """ an example of how to use the buffered pipeline, using a class instance
     """
 
     def __init__(self):
         addstage = ExampleAddClassStage()
-        BufferedPipeline.__init__(self, addstage)
+        BufferedHandshake.__init__(self, addstage)
 
 
 class TestInputAdd:
@@ -622,14 +625,14 @@ class ExampleStageDelayCls(StageCls):
         return m
 
 
-class ExampleBufDelayedPipe(BufferedPipeline):
+class ExampleBufDelayedPipe(BufferedHandshake):
 
     def __init__(self):
         stage = ExampleStageDelayCls(valid_trigger=2)
-        BufferedPipeline.__init__(self, stage, stage_ctl=True)
+        BufferedHandshake.__init__(self, stage, stage_ctl=True)
 
     def elaborate(self, platform):
-        m = BufferedPipeline.elaborate(self, platform)
+        m = BufferedHandshake.elaborate(self, platform)
         m.submodules.stage = self.stage
         return m
 
@@ -654,14 +657,14 @@ def test12_resultfn(o_data, expected, i, o):
 # Test 13
 ######################################################################
 
-class ExampleUnBufDelayedPipe(BufferedPipeline):
+class ExampleUnBufDelayedPipe(BufferedHandshake):
 
     def __init__(self):
         stage = ExampleStageDelayCls(valid_trigger=3)
-        BufferedPipeline.__init__(self, stage, stage_ctl=True)
+        BufferedHandshake.__init__(self, stage, stage_ctl=True)
 
     def elaborate(self, platform):
-        m = BufferedPipeline.elaborate(self, platform)
+        m = BufferedHandshake.elaborate(self, platform)
         m.submodules.stage = self.stage
         return m
 
@@ -706,6 +709,115 @@ class ExampleUnBufAdd1Pipe2(UnbufferedPipeline2):
         UnbufferedPipeline2.__init__(self, stage)
 
 
+######################################################################
+# Test 18
+######################################################################
+
+class PassThroughTest(PassThroughHandshake):
+
+    def iospecfn(self):
+        return Signal(16, "out")
+
+    def __init__(self):
+        stage = PassThroughStage(self.iospecfn)
+        PassThroughHandshake.__init__(self, stage)
+
+def test_identical_resultfn(o_data, expected, i, o):
+    res = expected
+    assert o_data == res, \
+                "%d-%d data %x not match %x\n" \
+                % (i, o, o_data, res)
+
+
+######################################################################
+# Test 19
+######################################################################
+
+class ExamplePassAdd1Pipe(PassThroughHandshake):
+
+    def __init__(self):
+        stage = ExampleStageCls()
+        PassThroughHandshake.__init__(self, stage)
+
+
+class ExampleBufPassThruPipe(ControlBase):
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        # XXX currently fails: any other permutation works fine.
+        # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
+        # also fails using UnbufferedPipeline as well
+        pipe1 = ExampleBufModeAdd1Pipe()
+        pipe2 = ExamplePassAdd1Pipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+
+######################################################################
+# Test 20
+######################################################################
+
+def iospecfn():
+    return Signal(16, name="din")
+
+class FIFOTest16(FIFOtest):
+
+
+    def __init__(self):
+        FIFOtest.__init__(self, iospecfn, 16, 2)
+
+
+######################################################################
+# Test 21
+######################################################################
+
+class ExampleFIFOPassThruPipe1(ControlBase):
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        pipe1 = FIFOTest16()
+        pipe2 = ExamplePassAdd1Pipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+
+######################################################################
+# Test 997
+######################################################################
+
+class ExampleBufPassThruPipe2(ControlBase):
+
+    def elaborate(self, platform):
+        m = ControlBase._elaborate(self, platform)
+
+        # XXX currently fails: any other permutation works fine.
+        # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
+        # also fails using UnbufferedPipeline as well
+        #pipe1 = ExampleUnBufAdd1Pipe()
+        #pipe2 = ExampleBufAdd1Pipe()
+        pipe1 = ExampleBufAdd1Pipe()
+        pipe2 = ExamplePassAdd1Pipe()
+
+        m.submodules.pipe1 = pipe1
+        m.submodules.pipe2 = pipe2
+
+        m.d.comb += self.connect([pipe1, pipe2])
+
+        return m
+
+
 ######################################################################
 # Test 998
 ######################################################################
@@ -733,11 +845,11 @@ class ExampleBufPipe3(ControlBase):
 # http://bugs.libre-riscv.org/show_bug.cgi?id=57
 ######################################################################
 
-class ExampleBufAdd1Pipe(BufferedPipeline):
+class ExampleBufAdd1Pipe(BufferedHandshake):
 
     def __init__(self):
         stage = ExampleStageCls()
-        BufferedPipeline.__init__(self, stage)
+        BufferedHandshake.__init__(self, stage)
 
 
 class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
@@ -772,7 +884,7 @@ class ExampleBufUnBufPipe(ControlBase):
 # Unit Tests
 ######################################################################
 
-num_tests = 100
+num_tests = 10
 
 if __name__ == '__main__':
     print ("test 1")
@@ -930,6 +1042,66 @@ if __name__ == '__main__':
     with open("test_unbufpipe17.il", "w") as f:
         f.write(vl)
 
+    print ("test 18")
+    dut = PassThroughTest()
+    data = data_chain1()
+    test = Test5(dut, test_identical_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_passthru18.il", "w") as f:
+        f.write(vl)
+
+    print ("test 19")
+    dut = ExampleBufPassThruPipe()
+    data = data_chain1()
+    test = Test5(dut, test9_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufpass19.il", "w") as f:
+        f.write(vl)
+
+    print ("test 20")
+    dut = FIFOTest16()
+    data = data_chain1()
+    test = Test5(dut, test_identical_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_fifo20.il", "w") as f:
+        f.write(vl)
+
+    print ("test 21")
+    dut = ExampleFIFOPassThruPipe1()
+    data = data_chain1()
+    test = Test5(dut, test12_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_fifopass21.il", "w") as f:
+        f.write(vl)
+
+    print ("test 997")
+    dut = ExampleBufPassThruPipe2()
+    data = data_chain1()
+    test = Test5(dut, test9_resultfn, data=data)
+    run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
+    ports = [dut.p.i_valid, dut.n.i_ready,
+             dut.n.o_valid, dut.p.o_ready] + \
+             [dut.p.i_data] + [dut.n.o_data]
+    vl = rtlil.convert(dut, ports=ports)
+    with open("test_bufpass997.il", "w") as f:
+        f.write(vl)
+
     print ("test 998 (fails, bug)")
     dut = ExampleBufPipe3()
     data = data_chain1()