from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
from example_buf_pipe import ExampleStageCls
-from example_buf_pipe import PrevControl, NextControl, BufferedPipeline
+from example_buf_pipe import PrevControl, NextControl, BufferedHandshake
from example_buf_pipe import StageChain, ControlBase, StageCls
from singlepipe import UnbufferedPipeline2
+from singlepipe import SimpleHandshake
+from singlepipe import PassThroughHandshake
+from singlepipe import PassThroughStage
+from singlepipe import FIFOtest
from random import randint, seed
-#seed(0)
+#seed(4)
def check_o_n_valid(dut, val):
send = True
else:
send = randint(0, send_range) != 0
+ #send = True
o_p_ready = yield self.dut.p.o_ready
if not o_p_ready:
yield
stall_range = randint(0, 3)
for j in range(randint(1,10)):
ready = randint(0, stall_range) != 0
- ready = True
+ #ready = True
yield self.dut.n.i_ready.eq(ready)
yield
o_n_valid = yield self.dut.n.o_valid
# Test 9
######################################################################
-class ExampleBufPipeChain2(BufferedPipeline):
+class ExampleBufPipeChain2(BufferedHandshake):
""" connects two stages together as a *single* combinatorial stage.
"""
def __init__(self):
stage1 = ExampleStageCls()
stage2 = ExampleStageCls()
combined = StageChain([stage1, stage2])
- BufferedPipeline.__init__(self, combined)
+ BufferedHandshake.__init__(self, combined)
def data_chain2():
UnbufferedPipeline.__init__(self, stage)
-class ExampleLTBufferedPipeDerived(BufferedPipeline):
+class ExampleLTBufferedPipeDerived(BufferedHandshake):
""" an example of how to use the buffered pipeline.
"""
def __init__(self):
stage = LTStageDerived()
- BufferedPipeline.__init__(self, stage)
+ BufferedHandshake.__init__(self, stage)
def test6_resultfn(o_data, expected, i, o):
return i.op1 + i.op2
-class ExampleBufPipeAddClass(BufferedPipeline):
+class ExampleBufPipeAddClass(BufferedHandshake):
""" an example of how to use the buffered pipeline, using a class instance
"""
def __init__(self):
addstage = ExampleAddClassStage()
- BufferedPipeline.__init__(self, addstage)
+ BufferedHandshake.__init__(self, addstage)
class TestInputAdd:
return (self.count == 1)# | (self.count == 3)
return Const(1)
- @property
- def d_valid(self):
+ def d_valid(self, i_ready):
return self.count == self.valid_trigger
return Const(1)
return m
-class ExampleBufDelayedPipe(BufferedPipeline):
+class ExampleBufDelayedPipe(BufferedHandshake):
def __init__(self):
- stage = ExampleStageDelayCls()
- BufferedPipeline.__init__(self, stage, stage_ctl=True)
+ stage = ExampleStageDelayCls(valid_trigger=2)
+ BufferedHandshake.__init__(self, stage, stage_ctl=True)
def elaborate(self, platform):
- m = BufferedPipeline.elaborate(self, platform)
+ m = BufferedHandshake.elaborate(self, platform)
m.submodules.stage = self.stage
return m
def data_chain1():
data = []
for i in range(num_tests):
- #data.append(1<<((i*2)%15))
- data.append(randint(0, 1<<16-2))
- print (hex(data[-1]))
+ data.append(1<<((i*3)%15))
+ #data.append(randint(0, 1<<16-2))
+ #print (hex(data[-1]))
return data
# Test 13
######################################################################
-class ExampleUnBufDelayedPipe(UnbufferedPipeline):
+class ExampleUnBufDelayedPipe(BufferedHandshake):
def __init__(self):
- stage = ExampleStageDelayCls()
- UnbufferedPipeline.__init__(self, stage, stage_ctl=True)
+ stage = ExampleStageDelayCls(valid_trigger=3)
+ BufferedHandshake.__init__(self, stage, stage_ctl=True)
def elaborate(self, platform):
- m = UnbufferedPipeline.elaborate(self, platform)
+ m = BufferedHandshake.elaborate(self, platform)
m.submodules.stage = self.stage
return m
######################################################################
-# Test 14
+# Test 15
######################################################################
-class ExampleBufPipe3(ControlBase):
- """ Example of how to do delayed pipeline, where the stage signals
- whether it is ready.
- """
+class ExampleBufModeAdd1Pipe(SimpleHandshake):
+
+ def __init__(self):
+ stage = ExampleStageCls()
+ SimpleHandshake.__init__(self, stage)
+
+
+######################################################################
+# Test 16
+######################################################################
+
+class ExampleBufModeUnBufPipe(ControlBase):
def elaborate(self, platform):
m = ControlBase._elaborate(self, platform)
- pipe1 = ExampleBufDelayedPipe()
- pipe2 = ExampleBufPipe()
+ pipe1 = ExampleBufModeAdd1Pipe()
+ pipe2 = ExampleBufAdd1Pipe()
m.submodules.pipe1 = pipe1
m.submodules.pipe2 = pipe2
return m
######################################################################
-# Test 15
+# Test 17
######################################################################
-class ExampleBufModeAdd1Pipe(BufferedPipeline):
+class ExampleUnBufAdd1Pipe2(UnbufferedPipeline2):
def __init__(self):
stage = ExampleStageCls()
- BufferedPipeline.__init__(self, stage, buffermode=False)
+ UnbufferedPipeline2.__init__(self, stage)
-class ExampleBufModeUnBufPipe(ControlBase):
+######################################################################
+# Test 18
+######################################################################
+
+class PassThroughTest(PassThroughHandshake):
+
+ def iospecfn(self):
+ return Signal(16, "out")
+
+ def __init__(self):
+ stage = PassThroughStage(self.iospecfn)
+ PassThroughHandshake.__init__(self, stage)
+
+def test_identical_resultfn(o_data, expected, i, o):
+ res = expected
+ assert o_data == res, \
+ "%d-%d data %x not match %x\n" \
+ % (i, o, o_data, res)
+
+
+######################################################################
+# Test 19
+######################################################################
+
+class ExamplePassAdd1Pipe(PassThroughHandshake):
+
+ def __init__(self):
+ stage = ExampleStageCls()
+ PassThroughHandshake.__init__(self, stage)
+
+
+class ExampleBufPassThruPipe(ControlBase):
def elaborate(self, platform):
m = ControlBase._elaborate(self, platform)
+ # XXX currently fails: any other permutation works fine.
+ # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
+ # also fails using UnbufferedPipeline as well
pipe1 = ExampleBufModeAdd1Pipe()
- pipe2 = ExampleBufAdd1Pipe()
+ pipe2 = ExamplePassAdd1Pipe()
m.submodules.pipe1 = pipe1
m.submodules.pipe2 = pipe2
return m
+######################################################################
+# Test 20
+######################################################################
+
+def iospecfn():
+ return Signal(16, name="din")
+
+class FIFOTest16(FIFOtest):
+
+
+ def __init__(self):
+ FIFOtest.__init__(self, iospecfn, 16, 2)
+
+
+######################################################################
+# Test 21
+######################################################################
+
+class ExampleFIFOPassThruPipe1(ControlBase):
+
+ def elaborate(self, platform):
+ m = ControlBase._elaborate(self, platform)
+
+ pipe1 = FIFOTest16()
+ pipe2 = ExamplePassAdd1Pipe()
+
+ m.submodules.pipe1 = pipe1
+ m.submodules.pipe2 = pipe2
+
+ m.d.comb += self.connect([pipe1, pipe2])
+
+ return m
+
+
+######################################################################
+# Test 997
+######################################################################
+
+class ExampleBufPassThruPipe2(ControlBase):
+
+ def elaborate(self, platform):
+ m = ControlBase._elaborate(self, platform)
+
+ # XXX currently fails: any other permutation works fine.
+ # p1=u,p2=b ok p1=u,p2=u ok p1=b,p2=b ok
+ # also fails using UnbufferedPipeline as well
+ #pipe1 = ExampleUnBufAdd1Pipe()
+ #pipe2 = ExampleBufAdd1Pipe()
+ pipe1 = ExampleBufAdd1Pipe()
+ pipe2 = ExamplePassAdd1Pipe()
+
+ m.submodules.pipe1 = pipe1
+ m.submodules.pipe2 = pipe2
+
+ m.d.comb += self.connect([pipe1, pipe2])
+
+ return m
+
+
+######################################################################
+# Test 998
+######################################################################
+
+class ExampleBufPipe3(ControlBase):
+ """ Example of how to do delayed pipeline, where the stage signals
+ whether it is ready.
+ """
+
+ def elaborate(self, platform):
+ m = ControlBase._elaborate(self, platform)
+
+ pipe1 = ExampleBufDelayedPipe()
+ pipe2 = ExampleBufPipe()
+
+ m.submodules.pipe1 = pipe1
+ m.submodules.pipe2 = pipe2
+
+ m.d.comb += self.connect([pipe1, pipe2])
+
+ return m
+
######################################################################
# Test 999 - XXX FAILS
# http://bugs.libre-riscv.org/show_bug.cgi?id=57
######################################################################
-class ExampleBufAdd1Pipe(BufferedPipeline):
+class ExampleBufAdd1Pipe(BufferedHandshake):
def __init__(self):
stage = ExampleStageCls()
- BufferedPipeline.__init__(self, stage)
+ BufferedHandshake.__init__(self, stage)
class ExampleUnBufAdd1Pipe(UnbufferedPipeline):
with open("test_unbufpipe13.il", "w") as f:
f.write(vl)
- print ("test 14")
- dut = ExampleBufPipe3()
+ print ("test 15")
+ dut = ExampleBufModeAdd1Pipe()
data = data_chain1()
- test = Test5(dut, test9_resultfn, data=data)
- run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
+ test = Test5(dut, test12_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf15.vcd")
ports = [dut.p.i_valid, dut.n.i_ready,
dut.n.o_valid, dut.p.o_ready] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
- with open("test_bufpipe14.il", "w") as f:
+ with open("test_bufunbuf15.il", "w") as f:
f.write(vl)
- print ("test 15)")
+ print ("test 16")
dut = ExampleBufModeUnBufPipe()
data = data_chain1()
test = Test5(dut, test9_resultfn, data=data)
- run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf999.vcd")
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufunbuf16.vcd")
ports = [dut.p.i_valid, dut.n.i_ready,
dut.n.o_valid, dut.p.o_ready] + \
[dut.p.i_data] + [dut.n.o_data]
vl = rtlil.convert(dut, ports=ports)
- with open("test_bufunbuf999.il", "w") as f:
+ with open("test_bufunbuf16.il", "w") as f:
+ f.write(vl)
+
+ print ("test 17")
+ dut = ExampleUnBufAdd1Pipe2()
+ data = data_chain1()
+ test = Test5(dut, test12_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_unbufpipe17.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_unbufpipe17.il", "w") as f:
+ f.write(vl)
+
+ print ("test 18")
+ dut = PassThroughTest()
+ data = data_chain1()
+ test = Test5(dut, test_identical_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_passthru18.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_passthru18.il", "w") as f:
+ f.write(vl)
+
+ print ("test 19")
+ dut = ExampleBufPassThruPipe()
+ data = data_chain1()
+ test = Test5(dut, test9_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass19.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufpass19.il", "w") as f:
+ f.write(vl)
+
+ print ("test 20")
+ dut = FIFOTest16()
+ data = data_chain1()
+ test = Test5(dut, test_identical_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifo20.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_fifo20.il", "w") as f:
+ f.write(vl)
+
+ print ("test 21")
+ dut = ExampleFIFOPassThruPipe1()
+ data = data_chain1()
+ test = Test5(dut, test12_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_fifopass21.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_fifopass21.il", "w") as f:
+ f.write(vl)
+
+ print ("test 997")
+ dut = ExampleBufPassThruPipe2()
+ data = data_chain1()
+ test = Test5(dut, test9_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpass997.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufpass997.il", "w") as f:
+ f.write(vl)
+
+ print ("test 998 (fails, bug)")
+ dut = ExampleBufPipe3()
+ data = data_chain1()
+ test = Test5(dut, test9_resultfn, data=data)
+ run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe14.vcd")
+ ports = [dut.p.i_valid, dut.n.i_ready,
+ dut.n.o_valid, dut.p.o_ready] + \
+ [dut.p.i_data] + [dut.n.o_data]
+ vl = rtlil.convert(dut, ports=ports)
+ with open("test_bufpipe14.il", "w") as f:
f.write(vl)
print ("test 999 (expected to fail, which is a bug)")
projects / ieee754fpu.git / blobdiff